Lab #3
Treehouse Encryption

This is an INDIVIDUAL lab. You must complete it by yourself.


The objectives of this lab are


This lab introduces more complex use of VHDL components. The overall premise is encryption of keyboard input based on a well-defined algorithm. Your job is to implement a decryption algorithm in C (optional), realize the given encryption algorithm in VHDL, and realize a hardware interface to the encryption algorithm in VHDL.


Your younger sibling is a member of a "secret club". The club's members think it would be cool to be able to send secret messages to each other. They are disappointed by the quality of the paper algorithms in their favourite mystery novels, which are weak against the energy and creativity of pesky siblings and parents.

The club approaches you, their own personal computer guru, to find a solution. Fortunately, they are quite well-funded, as one of the members' fathers has purchased FPGA setups for their clubhouses. They have commissioned you to create a hardware solution for their problem.

You have come up with the Treehouse Encryption Algorithm. Though terribly weak against serious attacks, it is sure to defeat the intruders interested in the club's secret messages.

The Treehouse Encryption Algorithm

The algorithm takes a 4-bit input
    <k3, k2, k1, k0>
and produces an 8-bit output
    <r7, r6, r5, r4, r3, r2, r1, r0>

The keyboard will generate the 4-bit input. In particular, you will use to the '0' to '9' keys of the number pad and the keys 'A' to 'F'. You will need to convert each of these key's scancode to its equivalent 4-bit value (e.g., we want the '0' key to produce the input "0000" and the 'F' key to produce the input "1111").

The steps in the algorithm are:

  1. Generate a bit vector p(7 downto 0) as described in the following table. Recall that the bit vector k(3 downto 0) is the circuit's input.

    Step 1

    p7 p6 p5 p4 p3 p2 p1 p0
    Operation k1 XOR k0 k0 k0 XOR k3 k3 k3 XOR k2 k2 k2 XOR k1 k1
  2. Generate a bit vector q(7 downto 0) according to the following table.

    Step 2

    q7 q6 q5 q4 q3 q2 q1 q0
    Operation p7 p6 XOR A p5 p4 XOR B p3 p2 XOR C p1 p0 XOR D

    In the above table, the values of A, B, C, and D depend on the values of p7 and p3. Implement a lookup table with the following contents:

    Lookup Table
    p7 p3 A B C D
    0 0 1 0 0 1
    0 1 0 1 1 0
    1 0 1 0 1 0
    1 1 0 1 0 1
  3. Generate a bit vector r(7 downto 0), the encryption circuit's output, by permuting the bit vector q. The permutation is based on the input count so far (mod 8). Assume that the first input corresponds to a count equal to 0.

    Step 3

    r7 r6 r5 r4 r3 r2 r1 r0
    0 q3 q5 q0 q1 q2 q6 q4
    1 q4 q7 q1 q0 q5 q3 q2 q6
    2 q3 q4 q6 q5 q0 q7 q2 q1
    3 q6 q2 q4 q7 q1 q0 q5 q3
    4 q0 q1 q7 q2 q4 q3 q6 q5
    5 q1 q7 q2 q0 q6 q5 q3 q4
    6 q5 q3 q4 q6 q7 q1 q0 q2
    7 q2 q0 q3 q1 q4 q5 q6 q7

We have implemented the Treehouse Encryption Algorithm in C as an example (encrypt.c). We have also traced a sample encryption.


We will not collect and mark these pre-lab tasks. That said, it is highly recommended that you complete them before beginning the lab. They are all designed to help you successfully complete it.


  1. Reading Assignments:
    1. Read and understand the lab assignment, the encrypt.c source code, and the description given on this page. If you have a reasonable grasp of how the encryption works, it will be easier to implement. Think about how your can modularize the encryption circuit into several components. Similarly, think about modularizing the interface. Think about how you will implement the required components in VHDL.
  2. Written Assignments:
    1. Write the decryption algorithm in C. The goal: familiarize yourself with the algorithm.
    2. Sketch a block diagram of the encryption circuit. Pay attention to matching the inputs and outputs of modules.
    3. Sketch a block diagram of the interface. Pay attention to matching the inputs and outputs of modules.



  1. Describe in VHDL the Treehouse Encryption Algorithm circuit. Your encryption circuit must work with the supplied testbench. To this end, it must conform to the following interface:

    entity encrypter is
      port (
        count: in  std_logic_vector(2 downto 0);
        hex:   in  std_logic_vector(3 downto 0);
        data:  out std_logic_vector(7 downto 0));
    end encrypter;
    Internally, the encrypter circuit should have a modular design. It should consist of multiple VHDL files where each defines/describes a component.

  2. Test your encrypter circuit with the supplied testbench.

  3. Describe in VHDL a 3-bit counter that you will later interface with your encryption circuit. Your counter circuit must work with the supplied testbench. To this end, it must conform to the following interface:

    entity counter is
      port (
        incr:  in  std_logic;
        reset: in  std_logic;
        count: out std_logic_vector(2 downto 0));
    end counter;
    The initial count must be "111" (7). Whenever the reset signal is high ('1'), the count should reset to "111" (7). Whenever the incr signal transitions from low-to-high, count should increment.

  4. Test your counter circuit with the supplied testbench.

  5. Describe in VHDL an interface to the encryption/counter circuit.

    Your interface must

    1. read input from the keyboard,
    2. interpret that keyboard input ('A' to 'F' and number pad keys '0' to '9') as hexadecimal,
    3. encrypt the interpreted keyboard input using the encrypter circuit, and
    4. display the encrypted result, as hexadecimal, using the two (lower) 7-segment LEDs.

    Given the complexity in interfacing your design with the keyboard, we provide a keyboard input component (kb_input.vhd). This module's inputs/outputs are

    You must convert the keyboard's scancode to a hexadecimal value for the encryption circuit.

    To convert the scancode to a hexadecimal value, you should use a process sensitive to the keyboard input module's rdy port. A pulse on the rdy port will indicate the need to re-evaluate scancode. To see how you might structure this VHDL code, take a look here.

    Like the other labs, you will need to write your own constraints file for the pin assignments. Refer to the XSA details page as necessary.

  6. Test your interfaced encrypter/counter on the board.

In this description, we have described three essential modules:

  1. encrypter,
  2. counter, and
  3. an interface to the encrypter/counter circuits.
Your design of the content of these modules is not limited. That said, we highly recommend that you break the modules down into smaller components wherever possible.


The lab reports can be submitted at any point up to the deadline to the TAs or to the CMPUT 329 drop box in the ground floor of CSC. The files that accompany the reports must be submitted electronically using astep (see E-Deliverables).



For the lab deliverables, you must submit all VHDL files used in your design (including those resources from this page that you have used) plus the waveform output from Sonata. Place all of the required files in a zip archive A hardcopy of your testbench output should be included with your lab report.

The archive must be submitted using the program astep as follows:

  % astep -c c329 -p lab3


Created by Paul Berube, 2001. Modified by Paras Mehta, 2003 by MacGregor, 2004, by Nikolaidis, 2006, by Boers, 2007, and by Boers, 2008.