This is an INDIVIDUAL lab. You must complete it by yourself.
This lab introduces more complex use of VHDL components. The overall premise is encryption of keyboard input based on a well-defined algorithm. Your job is to implement a decryption algorithm in C (optional), realize the given encryption algorithm in VHDL, and realize a hardware interface to the encryption algorithm in VHDL.
Your younger sibling is a member of a "secret club". The club's members think it would be cool to be able to send secret messages to each other. They are disappointed by the quality of the paper algorithms in their favourite mystery novels, which are weak against the energy and creativity of pesky siblings and parents.
The club approaches you, their own personal computer guru, to find a solution. Fortunately, they are quite well-funded, as one of the members' fathers has purchased FPGA setups for their clubhouses. They have commissioned you to create a hardware solution for their problem.
You have come up with the Treehouse Encryption Algorithm. Though terribly weak against serious attacks, it is sure to defeat the intruders interested in the club's secret messages.
The algorithm takes a 4-bit input
<k3, k2, k1, k0>
and produces an 8-bit output
<r7, r6, r5, r4, r3, r2, r1, r0>
The keyboard will generate the 4-bit input. In particular, you will use to the '0' to '9' keys of the number pad and the keys 'A' to 'F'. You will need to convert each of these key's scancode to its equivalent 4-bit value (e.g., we want the '0' key to produce the input "0000" and the 'F' key to produce the input "1111").
The steps in the algorithm are:
Generate a bit vector p(7 downto 0) as described in the following table. Recall that the bit vector k(3 downto 0) is the circuit's input.
|Operation||k1 XOR k0||k0||k0 XOR k3||k3||k3 XOR k2||k2||k2 XOR k1||k1|
Generate a bit vector q(7 downto 0) according to the following table.
|Operation||p7||p6 XOR A||p5||p4 XOR B||p3||p2 XOR C||p1||p0 XOR D|
In the above table, the values of A, B, C, and D depend on the values of p7 and p3. Implement a lookup table with the following contents:
Generate a bit vector r(7 downto 0), the encryption circuit's output, by permuting the bit vector q. The permutation is based on the input count so far (mod 8). Assume that the first input corresponds to a count equal to 0.
We have implemented the Treehouse Encryption Algorithm in C as an example (encrypt.c). We have also traced a sample encryption.
Describe in VHDL the Treehouse Encryption Algorithm circuit. Your encryption circuit must work with the supplied testbench. To this end, it must conform to the following interface:
entity encrypter is port ( count: in std_logic_vector(2 downto 0); hex: in std_logic_vector(3 downto 0); data: out std_logic_vector(7 downto 0)); end encrypter;Internally, the encrypter circuit should have a modular design. It should consist of multiple VHDL files where each defines/describes a component.
Test your encrypter circuit with the supplied testbench.
Describe in VHDL a 3-bit counter that you will later interface with your encryption circuit. Your counter circuit must work with the supplied testbench. To this end, it must conform to the following interface:
entity counter is port ( incr: in std_logic; reset: in std_logic; count: out std_logic_vector(2 downto 0)); end counter;The initial count must be "111" (7). Whenever the reset signal is high ('1'), the count should reset to "111" (7). Whenever the incr signal transitions from low-to-high, count should increment.
Test your counter circuit with the supplied testbench.
Describe in VHDL an interface to the encryption/counter circuit.
Your interface must
Given the complexity in interfacing your design with the keyboard, we provide a keyboard input component (kb_input.vhd). This module's inputs/outputs are
To convert the scancode to a hexadecimal value, you should use a process sensitive to the keyboard input module's rdy port. A pulse on the rdy port will indicate the need to re-evaluate scancode. To see how you might structure this VHDL code, take a look here.
Like the other labs, you will need to write your own constraints file for the pin assignments. Refer to the XSA details page as necessary.
Test your interfaced encrypter/counter on the board.
In this description, we have described three essential modules:
The lab reports can be submitted at any point up to the deadline to the TAs or to the CMPUT 329 drop box in the ground floor of CSC. The files that accompany the reports must be submitted electronically using astep (see E-Deliverables).
The kb_input module will produce the "make code" from this table. You do not need to worry about the "break code". All values are given in hexadecimal (i.e., x"2F" in VHDL). Also, since you are using numerical input, use the KP_# values rather than the regular numerical values.
Note that you can only assign to a signal in one process (or you will get errors about multiple drivers). You can read the value of a signal in any number of processes.
For the lab deliverables, you must submit all VHDL files used in your design (including those resources from this page that you have used) plus the waveform output from Sonata. Place all of the required files in a zip archive lab3.zip. A hardcopy of your testbench output should be included with your lab report.
The archive must be submitted using the program astep as follows:
% astep -c c329 -p lab3 lab3.zip